OpenMandrivaAssociation · Jul 23, 2024 · Jul 29, 2024 · Jul 30, 2024 · Aug 3, 2024 · Aug 9, 2024
diff --git a/.abf.yml b/.abf.yml
@@ -1,2 +1,2 @@
 sources:
-  mesa-24.1.4.tar.xz: ff468bdc04f865c01b7aa923ddd217850bc1a257
+  mesa-25.0.5.tar.xz: d6427cb320fcbd8bbe223ad69b16619391812fee
diff --git a/31950.patch b/31950.patch
@@ -0,0 +1,82 @@
+From 917e7e7df07b4523f1160e2a32d5e3ece3d74287 Mon Sep 17 00:00:00 2001
+From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Date: Mon, 4 Nov 2024 17:45:45 +1100
+Subject: [PATCH] dril: Fixup order of pixel formats in drilConfigs
+
+Having the RGB* formats before the BGR* formats in the table causes
+problems where under some circumstances, some applications end up
+with the wrong colors.
+
+The repro case for me is: Xvnc + mutter + chromium
+
+There was an existing comment in dri_fill_in_modes() which explained
+the problem. This was lost when dril_target.c was created.
+
+Fixes: ec7afd2c24c ("dril: rework config creation")
+Fixes: 3de62b2f9a6 ("gallium/dril: Compatibility stub for the legacy DRI loader interface")
+
+Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+---
+ src/gallium/targets/dril/dril_target.c | 36 +++++++++++++++++++-------
+ 1 file changed, 27 insertions(+), 9 deletions(-)
+
+diff --git a/src/gallium/targets/dril/dril_target.c b/src/gallium/targets/dril/dril_target.c
+index 672d50a418224..583728e409326 100644
+--- a/src/gallium/targets/dril/dril_target.c
++++ b/src/gallium/targets/dril/dril_target.c
+@@ -47,25 +47,43 @@
+    CONFIG_ZS(color, PIPE_FORMAT_Z16_UNORM), \
+    CONFIG_ZS(color, PIPE_FORMAT_NONE) \
+
++/*
++ * (copy of a comment in dri_screen.c:dri_fill_in_modes())
++ *
++ * The 32-bit RGBA format must not precede the 32-bit BGRA format.
++ * Likewise for RGBX and BGRX.  Otherwise, the GLX client and the GLX
++ * server may disagree on which format the GLXFBConfig represents,
++ * resulting in swapped color channels.
++ *
++ * The problem, as of 2017-05-30:
++ * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
++ * order and chooses the first __DRIconfig with the expected channel
++ * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
++ * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
++ *
++ * EGL does not suffer from this problem. It correctly compares the
++ * channel masks when matching EGLConfig to __DRIconfig.
++ */
++
+ static const struct gl_config drilConfigs[] = {
+-   CONFIG(PIPE_FORMAT_R8G8B8A8_UNORM),
+-   CONFIG(PIPE_FORMAT_R8G8B8X8_UNORM),
+    CONFIG(PIPE_FORMAT_B8G8R8A8_UNORM),
+    CONFIG(PIPE_FORMAT_B8G8R8X8_UNORM),
+-   CONFIG(PIPE_FORMAT_R10G10B10A2_UNORM),
+-   CONFIG(PIPE_FORMAT_R10G10B10X2_UNORM),
++   CONFIG(PIPE_FORMAT_R8G8B8A8_UNORM),
++   CONFIG(PIPE_FORMAT_R8G8B8X8_UNORM),
+    CONFIG(PIPE_FORMAT_B10G10R10A2_UNORM),
+    CONFIG(PIPE_FORMAT_B10G10R10X2_UNORM),
+-   CONFIG(PIPE_FORMAT_R5G6B5_UNORM),
+-   CONFIG(PIPE_FORMAT_R5G5B5A1_UNORM),
+-   CONFIG(PIPE_FORMAT_R5G5B5X1_UNORM),
+-   CONFIG(PIPE_FORMAT_R4G4B4A4_UNORM),
+-   CONFIG(PIPE_FORMAT_R4G4B4X4_UNORM),
++   CONFIG(PIPE_FORMAT_R10G10B10A2_UNORM),
++   CONFIG(PIPE_FORMAT_R10G10B10X2_UNORM),
+    CONFIG(PIPE_FORMAT_B5G6R5_UNORM),
+    CONFIG(PIPE_FORMAT_B5G5R5A1_UNORM),
+    CONFIG(PIPE_FORMAT_B5G5R5X1_UNORM),
+    CONFIG(PIPE_FORMAT_B4G4R4A4_UNORM),
+    CONFIG(PIPE_FORMAT_B4G4R4X4_UNORM),
++   CONFIG(PIPE_FORMAT_R5G6B5_UNORM),
++   CONFIG(PIPE_FORMAT_R5G5B5A1_UNORM),
++   CONFIG(PIPE_FORMAT_R5G5B5X1_UNORM),
++   CONFIG(PIPE_FORMAT_R4G4B4A4_UNORM),
++   CONFIG(PIPE_FORMAT_R4G4B4X4_UNORM),
+ };
+
+ #define RGB UTIL_FORMAT_COLORSPACE_RGB
+-- 
+GitLab
+
diff --git a/34001.patch b/34001.patch
@@ -0,0 +1,267 @@
+From f87d72152c92694d21165c2cd12e844f16755698 Mon Sep 17 00:00:00 2001
+From: David Rosca <david.rosca@amd.com>
+Date: Tue, 11 Mar 2025 13:41:30 +0100
+Subject: [PATCH 1/3] frontends/va: Support A8R8G8B8 format for processing
+
+Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
+Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34001>
+---
+ src/gallium/frontends/va/config.c  | 3 +++
+ src/gallium/frontends/va/surface.c | 3 +++
+ 2 files changed, 6 insertions(+)
+
+diff --git a/src/gallium/frontends/va/config.c b/src/gallium/frontends/va/config.c
+index aceafe8d7f997..e05096b5df5c3 100644
+--- a/src/gallium/frontends/va/config.c
++++ b/src/gallium/frontends/va/config.c
+@@ -174,6 +174,9 @@ static unsigned int get_screen_supported_va_rt_formats(struct pipe_screen *pscre
+                                           profile,
+                                           entrypoint) ||
+        pscreen->is_video_format_supported(pscreen, PIPE_FORMAT_B8G8R8X8_UNORM,
++                                          profile,
++                                          entrypoint) ||
++       pscreen->is_video_format_supported(pscreen, PIPE_FORMAT_A8R8G8B8_UNORM,
+                                           profile,
+                                           entrypoint))
+       supported_rt_formats |= VA_RT_FORMAT_RGB32;
+diff --git a/src/gallium/frontends/va/surface.c b/src/gallium/frontends/va/surface.c
+index a56696e67bf5a..c82b7cd8d2651 100644
+--- a/src/gallium/frontends/va/surface.c
++++ b/src/gallium/frontends/va/surface.c
+@@ -574,6 +574,7 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx, VAConfigID config_id,
+       vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_B8G8R8A8_UNORM, attribs, &i);
+       vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_R8G8B8X8_UNORM, attribs, &i);
+       vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_B8G8R8X8_UNORM, attribs, &i);
++      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_A8R8G8B8_UNORM, attribs, &i);
+    }
+
+    if (config->rt_format & VA_RT_FORMAT_RGB32_10) {
+@@ -1576,6 +1577,8 @@ static uint32_t pipe_format_to_drm_format(enum pipe_format format)
+       return DRM_FORMAT_XRGB8888;
+    case PIPE_FORMAT_R8G8B8X8_UNORM:
+       return DRM_FORMAT_XBGR8888;
++   case PIPE_FORMAT_A8R8G8B8_UNORM:
++      return DRM_FORMAT_BGRA8888;
+    case PIPE_FORMAT_B10G10R10A2_UNORM:
+       return DRM_FORMAT_ARGB2101010;
+    case PIPE_FORMAT_R10G10B10A2_UNORM:
+-- 
+GitLab
+
+
+From 47a9312a5d2b188f6c875777c5a41070c835f07d Mon Sep 17 00:00:00 2001
+From: David Rosca <david.rosca@amd.com>
+Date: Tue, 11 Mar 2025 13:41:54 +0100
+Subject: [PATCH 2/3] frontends/va: Use ARGB as default fourcc for RGB32 RT
+ format
+
+This matches Intel driver and is what Chromium expects.
+
+Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
+Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34001>
+---
+ src/gallium/frontends/va/surface.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/gallium/frontends/va/surface.c b/src/gallium/frontends/va/surface.c
+index c82b7cd8d2651..27f3914d3ae44 100644
+--- a/src/gallium/frontends/va/surface.c
++++ b/src/gallium/frontends/va/surface.c
+@@ -1064,7 +1064,7 @@ rt_format_to_fourcc(uint32_t format)
+    case VA_RT_FORMAT_RGBP:
+       return VA_FOURCC_RGBP;
+    case VA_RT_FORMAT_RGB32:
+-      return VA_FOURCC_BGRA;
++      return VA_FOURCC_ARGB;
+    case VA_RT_FORMAT_RGB32_10:
+       return VA_FOURCC_X2R10G10B10;
+    default:
+-- 
+GitLab
+
+
+From 43c99d3928b31e7b2b0fc25250b45fade83f8a06 Mon Sep 17 00:00:00 2001
+From: David Rosca <david.rosca@amd.com>
+Date: Tue, 11 Mar 2025 13:58:48 +0100
+Subject: [PATCH 3/3] frontends/va: Don't filter supported formats according to
+ config RT format
+
+This matches Intel driver. Chromium always sets RT format to YUV420
+which would cause us to not report other formats as supported.
+Only check that the RT format is actually supported when creating
+config, but don't limit supported surface formats.
+
+Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
+Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34001>
+---
+ src/gallium/frontends/va/config.c     | 20 ++-----
+ src/gallium/frontends/va/surface.c    | 81 +++++++++++++--------------
+ src/gallium/frontends/va/va_private.h |  1 -
+ 3 files changed, 43 insertions(+), 59 deletions(-)
+
+diff --git a/src/gallium/frontends/va/config.c b/src/gallium/frontends/va/config.c
+index e05096b5df5c3..588b69bfaf2c4 100644
+--- a/src/gallium/frontends/va/config.c
++++ b/src/gallium/frontends/va/config.c
+@@ -640,9 +640,7 @@ vlVaCreateConfig(VADriverContextP ctx, VAProfile profile, VAEntrypoint entrypoin
+                                                                 config->entrypoint);
+       for (int i = 0; i < num_attribs; i++) {
+          if (attrib_list[i].type == VAConfigAttribRTFormat) {
+-            if (attrib_list[i].value & supported_rt_formats) {
+-               config->rt_format = attrib_list[i].value;
+-            } else {
++            if (!(attrib_list[i].value & supported_rt_formats)) {
+                FREE(config);
+                return VA_STATUS_ERROR_UNSUPPORTED_RT_FORMAT;
+             }
+@@ -653,10 +651,6 @@ vlVaCreateConfig(VADriverContextP ctx, VAProfile profile, VAEntrypoint entrypoin
+          }
+       }
+
+-      /* Default value if not specified in the input attributes. */
+-      if (!config->rt_format)
+-         config->rt_format = supported_rt_formats;
+-
+       mtx_lock(&drv->mutex);
+       *config_id = handle_table_add(drv->htab, config);
+       mtx_unlock(&drv->mutex);
+@@ -733,9 +727,7 @@ vlVaCreateConfig(VADriverContextP ctx, VAProfile profile, VAEntrypoint entrypoin
+          }
+       }
+       if (attrib_list[i].type == VAConfigAttribRTFormat) {
+-         if (attrib_list[i].value & supported_rt_formats) {
+-            config->rt_format = attrib_list[i].value;
+-         } else {
++         if (!(attrib_list[i].value & supported_rt_formats)) {
+             FREE(config);
+             return VA_STATUS_ERROR_UNSUPPORTED_RT_FORMAT;
+          }
+@@ -756,10 +748,6 @@ vlVaCreateConfig(VADriverContextP ctx, VAProfile profile, VAEntrypoint entrypoin
+       }
+    }
+
+-   /* Default value if not specified in the input attributes. */
+-   if (!config->rt_format)
+-      config->rt_format = supported_rt_formats;
+-
+    mtx_lock(&drv->mutex);
+    *config_id = handle_table_add(drv->htab, config);
+    mtx_unlock(&drv->mutex);
+@@ -836,7 +824,9 @@ vlVaQueryConfigAttributes(VADriverContextP ctx, VAConfigID config_id, VAProfile
+
+    *num_attribs = 1;
+    attrib_list[0].type = VAConfigAttribRTFormat;
+-   attrib_list[0].value = config->rt_format;
++   attrib_list[0].value = get_screen_supported_va_rt_formats(drv->pipe->screen,
++                                                             config->profile,
++                                                             config->entrypoint);
+
+    return VA_STATUS_SUCCESS;
+ }
+diff --git a/src/gallium/frontends/va/surface.c b/src/gallium/frontends/va/surface.c
+index 27f3914d3ae44..cfbc5845e3666 100644
+--- a/src/gallium/frontends/va/surface.c
++++ b/src/gallium/frontends/va/surface.c
+@@ -540,49 +540,44 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx, VAConfigID config_id,
+
+    i = 0;
+
+-   if (config->rt_format & VA_RT_FORMAT_YUV420) {
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_NV12, attribs, &i);
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_YV12, attribs, &i);
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_IYUV, attribs, &i);
+-   }
+-
+-   if (config->rt_format & VA_RT_FORMAT_YUV420_10) {
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_P010, attribs, &i);
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_P016, attribs, &i);
+-   }
+-
+-   if (config->rt_format & VA_RT_FORMAT_YUV420_12)
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_P012, attribs, &i);
+-
+-   if (config->rt_format & VA_RT_FORMAT_YUV400)
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_Y8_400_UNORM, attribs, &i);
+-
+-   if (config->rt_format & VA_RT_FORMAT_YUV422) {
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_UYVY, attribs, &i);
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_YUYV, attribs, &i);
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_Y8_U8_V8_440_UNORM, attribs, &i);
+-   }
+-
+-   if (config->rt_format & VA_RT_FORMAT_YUV444)
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_Y8_U8_V8_444_UNORM, attribs, &i);
+-
+-   if (config->rt_format & VA_RT_FORMAT_RGBP)
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_R8_G8_B8_UNORM, attribs, &i);
+-
+-   if (config->rt_format & VA_RT_FORMAT_RGB32) {
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_R8G8B8A8_UNORM, attribs, &i);
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_B8G8R8A8_UNORM, attribs, &i);
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_R8G8B8X8_UNORM, attribs, &i);
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_B8G8R8X8_UNORM, attribs, &i);
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_A8R8G8B8_UNORM, attribs, &i);
+-   }
+-
+-   if (config->rt_format & VA_RT_FORMAT_RGB32_10) {
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_R10G10B10A2_UNORM, attribs, &i);
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_B10G10R10A2_UNORM, attribs, &i);
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_R10G10B10X2_UNORM, attribs, &i);
+-      vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_B10G10R10X2_UNORM, attribs, &i);
+-   }
++   /* VA_RT_FORMAT_YUV420 */
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_NV12, attribs, &i);
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_YV12, attribs, &i);
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_IYUV, attribs, &i);
++
++   /* VA_RT_FORMAT_YUV420_10 */
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_P010, attribs, &i);
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_P016, attribs, &i);
++
++   /* VA_RT_FORMAT_YUV420_12 */
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_P012, attribs, &i);
++
++   /* VA_RT_FORMAT_YUV400 */
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_Y8_400_UNORM, attribs, &i);
++
++   /* VA_RT_FORMAT_YUV422 */
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_UYVY, attribs, &i);
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_YUYV, attribs, &i);
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_Y8_U8_V8_440_UNORM, attribs, &i);
++
++   /* VA_RT_FORMAT_YUV444 */
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_Y8_U8_V8_444_UNORM, attribs, &i);
++
++   /* VA_RT_FORMAT_RGBP */
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_R8_G8_B8_UNORM, attribs, &i);
++
++   /* VA_RT_FORMAT_RGB32 */
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_R8G8B8A8_UNORM, attribs, &i);
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_B8G8R8A8_UNORM, attribs, &i);
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_R8G8B8X8_UNORM, attribs, &i);
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_B8G8R8X8_UNORM, attribs, &i);
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_A8R8G8B8_UNORM, attribs, &i);
++
++   /* VA_RT_FORMAT_RGB32_10 */
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_R10G10B10A2_UNORM, attribs, &i);
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_B10G10R10A2_UNORM, attribs, &i);
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_R10G10B10X2_UNORM, attribs, &i);
++   vlVaAddSurfaceFormat(pscreen, config, PIPE_FORMAT_B10G10R10X2_UNORM, attribs, &i);
+
+    attribs[i].type = VASurfaceAttribMemoryType;
+    attribs[i].value.type = VAGenericValueTypeInteger;
+diff --git a/src/gallium/frontends/va/va_private.h b/src/gallium/frontends/va/va_private.h
+index 81e04a23e0d65..e1acc1843a155 100644
+--- a/src/gallium/frontends/va/va_private.h
++++ b/src/gallium/frontends/va/va_private.h
+@@ -447,7 +447,6 @@ typedef struct {
+    enum pipe_video_profile profile;
+    enum pipe_video_entrypoint entrypoint;
+    enum pipe_h2645_enc_rate_control_method rc;
+-   unsigned int rt_format;
+ } vlVaConfig;
+
+ typedef struct vlVaSurface {
+-- 
+GitLab
+
diff --git a/mesa-20.3.0-meson-radeon-arm-riscv-ppc.patch b/mesa-20.3.0-meson-radeon-arm-riscv-ppc.patch
@@ -1,30 +1,30 @@
-diff -up mesa-24.1.0-rc1/meson.build.4~ mesa-24.1.0-rc1/meson.build
---- mesa-24.1.0-rc1/meson.build.4~	2024-04-26 04:19:17.527914094 +0200
-+++ mesa-24.1.0-rc1/meson.build	2024-04-26 04:22:16.081486445 +0200
-@@ -150,9 +150,9 @@ if gallium_drivers.contains('auto')
+diff -up mesa-25.0.0-rc2/meson.build.5~ mesa-25.0.0-rc2/meson.build
+--- mesa-25.0.0-rc2/meson.build.5~	2025-02-05 22:17:27.159187978 +0100
++++ mesa-25.0.0-rc2/meson.build	2025-02-05 22:20:42.184061633 +0100
+@@ -142,7 +142,7 @@ if gallium_drivers.contains('auto')
        gallium_drivers = [
          'v3d', 'vc4', 'freedreno', 'etnaviv', 'nouveau', 'svga',
-         'tegra', 'virgl', 'lima', 'panfrost', 'swrast', 'iris',
+         'tegra', 'virgl', 'lima', 'panfrost', 'llvmpipe', 'softpipe', 'iris',
 -        'zink'
 +        'zink', 'r300', 'r600', 'radeonsi'
        ]
--    elif ['mips', 'mips64', 'riscv32', 'riscv64'].contains(host_machine.cpu_family())
-+    elif ['mips', 'mips64', 'riscv32', 'riscv64', 'ppc64', 'ppc64le'].contains(host_machine.cpu_family())
+     elif ['mips', 'mips64', 'ppc', 'ppc64', 'riscv32', 'riscv64'].contains(host_machine.cpu_family())
        gallium_drivers = [
-         'r300', 'r600', 'radeonsi', 'nouveau', 'virgl', 'swrast', 'zink'
-       ]
-@@ -222,12 +222,8 @@ if _vulkan_drivers.contains('auto')
+@@ -228,13 +228,11 @@ _vulkan_drivers = get_option('vulkan-dri
+ if _vulkan_drivers.contains('auto')
    if system_has_kms_drm
      if host_machine.cpu_family().startswith('x86')
-       _vulkan_drivers = ['amd', 'intel', 'intel_hasvk', 'nouveau', 'swrast']
--    elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
--      _vulkan_drivers = ['swrast', 'intel']
--    elif ['mips', 'mips64', 'riscv32', 'riscv64'].contains(host_machine.cpu_family())
+-      _vulkan_drivers = ['amd', 'intel', 'intel_hasvk', 'nouveau', 'swrast']
++      _vulkan_drivers = ['amd', 'intel', 'intel_hasvk', 'nouveau', 'swrast', 'virtio']
+     elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
+-      _vulkan_drivers = ['swrast', 'intel', 'panfrost']
+-    elif ['mips', 'mips64', 'ppc', 'ppc64', 'riscv32', 'riscv64'].contains(host_machine.cpu_family())
 -      _vulkan_drivers = ['amd', 'swrast']
 -    elif ['loongarch64'].contains(host_machine.cpu_family())
 -      _vulkan_drivers = ['amd', 'swrast']
-+    elif ['arm', 'aarch64', 'mips', 'mips64', 'riscv32', 'riscv64', 'loongarch64'].contains(host_machine.cpu_family())
-+      _vulkan_drivers = ['amd', 'swrast', 'intel']
++      _vulkan_drivers = ['swrast', 'intel', 'panfrost', 'amd', 'freedreno', 'broadcom', 'virtio', 'imagination-experimental', 'nouveau']
++    elif ['mips', 'mips64', 'ppc', 'ppc64', 'riscv32', 'riscv64', 'loongarch64'].contains(host_machine.cpu_family())
++      _vulkan_drivers = ['amd', 'swrast', 'intel', 'virtio', 'imagination-experimental', 'nouveau']
      else
        error('Unknown architecture @0@. Please pass -Dvulkan-drivers to set driver options. Patches gladly accepted to fix this.'.format(
              host_machine.cpu_family()))
diff --git a/mesa-23.3.0-rc4-panfrost-enable-gl3-by-default.patch b/mesa-23.3.0-rc4-panfrost-enable-gl3-by-default.patch
@@ -1,31 +1,31 @@
-diff -up mesa-23.3.0-rc4/src/gallium/drivers/panfrost/pan_screen.c.omv~ mesa-23.3.0-rc4/src/gallium/drivers/panfrost/pan_screen.c
---- mesa-23.3.0-rc4/src/gallium/drivers/panfrost/pan_screen.c.omv~	2023-11-16 23:53:28.826244553 +0100
-+++ mesa-23.3.0-rc4/src/gallium/drivers/panfrost/pan_screen.c	2023-11-16 23:55:01.985156880 +0100
-@@ -63,7 +63,7 @@ static const struct debug_named_value pa
+diff -up mesa-25.0.0-rc2/src/gallium/drivers/panfrost/pan_screen.c.4~ mesa-25.0.0-rc2/src/gallium/drivers/panfrost/pan_screen.c
+--- mesa-25.0.0-rc2/src/gallium/drivers/panfrost/pan_screen.c.4~	2025-02-05 22:15:47.469618569 +0100
++++ mesa-25.0.0-rc2/src/gallium/drivers/panfrost/pan_screen.c	2025-02-05 22:16:53.141439864 +0100
+@@ -65,7 +65,7 @@ static const struct debug_named_value pa
     {"dirty",      PAN_DBG_DIRTY,    "Always re-emit all state"},
     {"sync",       PAN_DBG_SYNC,     "Wait for each job's completion and abort on GPU faults"},
     {"nofp16",     PAN_DBG_NOFP16,    "Disable 16-bit support"},
 -   {"gl3",        PAN_DBG_GL3,      "Enable experimental GL 3.x implementation, up to 3.3"},
 +   {"nogl3",      PAN_DBG_NOGL3,    "Disable experimental GL 3.x implementation, up to 3.3"},
     {"noafbc",     PAN_DBG_NO_AFBC,  "Disable AFBC support"},
-    {"crc",        PAN_DBG_CRC,      "Enable transaction elimination"},
+    {"nocrc",      PAN_DBG_NO_CRC,   "Disable transaction elimination"},
     {"msaa16",     PAN_DBG_MSAA16,   "Enable MSAA 8x and 16x support"},
-@@ -102,7 +102,7 @@ panfrost_get_param(struct pipe_screen *s
-    struct panfrost_device *dev = pan_device(screen);
+@@ -567,7 +567,7 @@ panfrost_init_screen_caps(struct panfros
+    struct panfrost_device *dev = &screen->dev;
 
     /* Our GL 3.x implementation is WIP */
 -   bool is_gl3 = dev->debug & PAN_DBG_GL3;
 +   bool is_gl3 = (dev->debug & PAN_DBG_NOGL3) == 0;
 
     /* Native MRT is introduced with v5 */
     bool has_mrt = (dev->arch >= 5);
-diff -up mesa-23.3.0-rc4/src/panfrost/lib/pan_util.h.omv~ mesa-23.3.0-rc4/src/panfrost/lib/pan_util.h
---- mesa-23.3.0-rc4/src/panfrost/lib/pan_util.h.omv~	2023-11-16 23:52:59.918964277 +0100
-+++ mesa-23.3.0-rc4/src/panfrost/lib/pan_util.h	2023-11-16 23:53:17.097130660 +0100
+diff -up mesa-25.0.0-rc2/src/panfrost/lib/pan_util.h.4~ mesa-25.0.0-rc2/src/panfrost/lib/pan_util.h
+--- mesa-25.0.0-rc2/src/panfrost/lib/pan_util.h.4~	2025-02-05 22:15:47.469769764 +0100
++++ mesa-25.0.0-rc2/src/panfrost/lib/pan_util.h	2025-02-05 22:17:10.908465345 +0100
 @@ -40,7 +40,7 @@
  /* 0x20 unused */
  #define PAN_DBG_NOFP16  0x0040
- #define PAN_DBG_CRC     0x0080
+ #define PAN_DBG_NO_CRC  0x0080
 -#define PAN_DBG_GL3     0x0100
 +#define PAN_DBG_NOGL3   0x0100
  #define PAN_DBG_NO_AFBC 0x0200

diff --git a/mesa-24-llvmspirv-detection.patch b/mesa-24-llvmspirv-detection.patch
@@ -1,11 +1,12 @@
-diff -up mesa-24.0.0-rc3/meson.build.omv~ mesa-24.0.0-rc3/meson.build
---- mesa-24.0.0-rc3/meson.build.omv~	2024-01-27 18:09:38.093727414 +0100
-+++ mesa-24.0.0-rc3/meson.build	2024-01-27 18:10:04.953994095 +0100
-@@ -1840,7 +1840,7 @@ with_opencl_spirv = (_opencl != 'disable
- if with_opencl_spirv
+diff -up mesa-25.0.0-rc2/meson.build.6~ mesa-25.0.0-rc2/meson.build
+--- mesa-25.0.0-rc2/meson.build.6~	2025-02-05 22:21:04.522649744 +0100
++++ mesa-25.0.0-rc2/meson.build	2025-02-05 22:21:34.301575614 +0100
+@@ -1856,7 +1856,8 @@ pre_args += '-DGALLIVM_USE_ORCJIT=@0@'.f
+ if with_clc
    chosen_llvm_version_array = dep_llvm.version().split('.')
    chosen_llvm_version_major = chosen_llvm_version_array[0].to_int()
 -  chosen_llvm_version_minor = chosen_llvm_version_array[1].to_int()
++  #chosen_llvm_version_minor = chosen_llvm_version_array[1].to_int()
 +  chosen_llvm_version_minor = 0
 
    # Require an SPIRV-LLVM-Translator version compatible with the chosen LLVM

diff --git a/mesa-24.0-llvmspirvlib-version-check.patch b/mesa-24.0-llvmspirvlib-version-check.patch
@@ -1,13 +1,12 @@
-diff -up mesa-24.0.0/meson.build.omv~ mesa-24.0.0/meson.build
---- mesa-24.0.0/meson.build.omv~	2024-02-03 16:34:53.652011092 +0100
-+++ mesa-24.0.0/meson.build	2024-02-03 16:35:50.452562741 +0100
-@@ -1857,8 +1857,7 @@ if with_opencl_spirv
-
+diff -up mesa-24.3.0-rc1/meson.build.omv~ mesa-24.3.0-rc1/meson.build
+--- mesa-24.3.0-rc1/meson.build.omv~	2024-11-10 17:24:02.589758678 +0100
++++ mesa-24.3.0-rc1/meson.build	2024-11-10 17:24:30.870073527 +0100
+@@ -1858,7 +1858,7 @@ if with_clover_spirv or with_clc
    _llvmspirvlib_version = [
      _llvmspirvlib_min_version,
--    '>= @0@.@1@'.format(chosen_llvm_version_major, chosen_llvm_version_minor),
+     '>= @0@.@1@'.format(chosen_llvm_version_major, chosen_llvm_version_minor),
 -    '< @0@.@1@'.format(chosen_llvm_version_major, chosen_llvm_version_minor + 1) ]
-+    '>= @0@.@1@'.format(chosen_llvm_version_major, chosen_llvm_version_minor) ]
++    '< @0@.@1@'.format(chosen_llvm_version_major + 1, chosen_llvm_version_minor + 1) ]
 
-   dep_spirv_tools = dependency('SPIRV-Tools', required : true, version : '>= 2018.0')
    # LLVMSPIRVLib is available at https://github.com/KhronosGroup/SPIRV-LLVM-Translator
+   dep_llvmspirvlib = dependency('LLVMSPIRVLib', required : true, version : _llvmspirvlib_version)
diff --git a/mesa-24.1-find-opencl-c-base.h.patch b/mesa-24.1-find-opencl-c-base.h.patch
@@ -1,11 +1,13 @@
-diff -up mesa-24.1.0-rc1/src/intel/shaders/meson.build.omv~ mesa-24.1.0-rc1/src/intel/shaders/meson.build
---- mesa-24.1.0-rc1/src/intel/shaders/meson.build.omv~	2024-04-26 06:31:25.951601137 +0200
-+++ mesa-24.1.0-rc1/src/intel/shaders/meson.build	2024-04-26 06:31:45.319852869 +0200
-@@ -65,6 +65,7 @@ foreach gen : intel_shaders_gens
+diff -up mesa-25.0.0-rc2/src/intel/shaders/meson.build.3~ mesa-25.0.0-rc2/src/intel/shaders/meson.build
+--- mesa-25.0.0-rc2/src/intel/shaders/meson.build.3~	2025-02-05 22:13:21.450833576 +0100
++++ mesa-25.0.0-rc2/src/intel/shaders/meson.build	2025-02-05 22:15:31.953461583 +0100
+@@ -51,6 +51,9 @@ foreach gen : intel_shaders_gens
        '-I' + join_paths(dir_source_root, 'src/intel'),
        '-I' + join_paths(meson.project_build_root(), 'src/intel'),
        '-I' + join_paths(dir_source_root, 'src/intel/genxml'),
 +      '-I/usr/lib64/clang/18/include',
++      '-I/usr/lib64/clang/19/include',
++      '-I/usr/lib64/clang/20/include',
      ],
-     env: ['MESA_SHADER_CACHE_DISABLE=true'],
-     depends : [dep_prog_intel_clc, gen_cl_xml_pack],
+     depends : [gen_cl_xml_pack, intel_dev_wa_src],
+   )
diff --git a/mesa-buildsystem-improvements.patch b/mesa-buildsystem-improvements.patch
@@ -1,7 +1,7 @@
-diff -up mesa-24.1.0-rc1/meson.build.7~ mesa-24.1.0-rc1/meson.build
---- mesa-24.1.0-rc1/meson.build.7~	2024-04-26 04:27:02.456009045 +0200
-+++ mesa-24.1.0-rc1/meson.build	2024-04-26 04:27:37.076314053 +0200
-@@ -139,6 +139,12 @@ system_has_kms_drm = ['openbsd', 'netbsd
+diff -up mesa-24.2.0-rc1/meson.build.7~ mesa-24.2.0-rc1/meson.build
+--- mesa-24.2.0-rc1/meson.build.7~	2024-07-22 17:30:43.078816172 +0200
++++ mesa-24.2.0-rc1/meson.build	2024-07-22 17:40:59.460820444 +0200
+@@ -122,6 +122,12 @@ system_has_kms_drm = ['openbsd', 'netbsd
 
  gallium_drivers = get_option('gallium-drivers')
  if gallium_drivers.contains('auto')
@@ -12,9 +12,9 @@ diff -up mesa-24.1.0-rc1/meson.build.7~ mesa-24.1.0-rc1/meson.build
 +    endif
 +  endforeach
    if system_has_kms_drm
-     # TODO: PPC, Sparc
+     # TODO: Sparc
      if ['x86', 'x86_64'].contains(host_machine.cpu_family())
-@@ -172,6 +178,11 @@ if gallium_drivers.contains('auto')
+@@ -155,6 +161,11 @@ if gallium_drivers.contains('auto')
      error('Unknown OS @0@. Please pass -Dgallium-drivers to set driver options. Patches gladly accepted to fix this.'.format(
            host_machine.system()))
    endif
@@ -26,7 +26,7 @@ diff -up mesa-24.1.0-rc1/meson.build.7~ mesa-24.1.0-rc1/meson.build
  elif gallium_drivers.contains('all')
     # Build-test everything except for i915, which depends on libdrm-intel which
     # is not available on non-Intel distros.
-@@ -219,6 +230,12 @@ with_gallium_kmsro = system_has_kms_drm
+@@ -215,6 +226,12 @@ with_gallium_kmsro = system_has_kms_drm
 
  _vulkan_drivers = get_option('vulkan-drivers')
  if _vulkan_drivers.contains('auto')
@@ -38,8 +38,8 @@ diff -up mesa-24.1.0-rc1/meson.build.7~ mesa-24.1.0-rc1/meson.build
 +  endforeach
    if system_has_kms_drm
      if host_machine.cpu_family().startswith('x86')
-       _vulkan_drivers = ['amd', 'intel', 'intel_hasvk', 'nouveau', 'swrast']
-@@ -235,6 +252,11 @@ if _vulkan_drivers.contains('auto')
+       _vulkan_drivers = ['amd', 'intel', 'intel_hasvk', 'nouveau', 'swrast', 'virtio']
+@@ -233,6 +250,11 @@ if _vulkan_drivers.contains('auto')
      error('Unknown OS @0@. Please pass -Dvulkan-drivers to set driver options. Patches gladly accepted to fix this.'.format(
            host_machine.system()))
    endif

diff --git a/mesa.spec b/mesa.spec